1. Field of the Invention
The present invention relates to a nonvolatile semiconductor memory device having a memory cell of a stack gate structure.
2. Description of the Related Art
In a nonvolatile semiconductor memory device such as a NAND type flash memory, a memory cell (cell transistor) has a stack gate structure. The stack gate structure denotes a structure in which a floating gate electrode and a control gate electrode are stacked on a channel between a source diffusion layer and a drain diffusion layer.
The programming/erasing with respect to such a memory cell is carried out by applying a high electric field to a tunnel insulation film between a channel and the floating gate electrode, and then, exchanging an electric charge (for example, an electron) therebetween. Namely, an amount of the electric charge in the floating gate electrode is changed, thereby shifting a threshold voltage of the memory cell, and then, storing data (“0” or “1”).
Here, in order to improve efficiency of the programming/erasing, it is necessary to increase a coupling ratio β of the memory cell, and further, reduce a leakage current at the time of the programming/erasing.
The coupling ratio β of the memory cell is defined by a ratio of a voltage change of the floating gate electrode to a voltage change of the control gate electrode. When this coupling ratio is expressed by a capacitance ratio, β=CIPD/Ctot is established.
In this formula, Ctot denotes a sum of capacitance between the control gate electrode and the channel, and CIPD denotes a capacitance between the control gate electrode and the floating gate electrode.
Conventionally, with respect to an increase of the coupling ratio β, such an increase has been achieved by contriving a material for an insulation film (a so called inter-poly insulation film) that is provided between the floating gate electrode and the control gate electrode. For example, an ONO (SiO2/SiN/SiO2) film has been used as an inter-poly insulation film.
Recently, instead of the above described ONO film, there has been actively made a research on using a material having a higher dielectric constant (high-k) than that of the ONO film as the inter-poly insulation film.
At the current stage, as a high dielectric material, there are proposed an aluminum oxide film (Al2O3), a hafnium oxide film (HfO2), and a mixture or mixed crystal thereof (hafnium aluminate: HfAlOx) or the like.
These materials have good compatibility with a silicon process, can cope with memory cell downsizing, and are greatly expected for its extended use in the future.
However, when such a high dielectric material is used as an inter-poly insulation film, there is a problem that a leakage current between the floating gate electrode and the control gate electrode at the time of the programming/erasing exceeds a reference value, resulting in impaired memory cell characteristics.